1. Field of the Invention
The present invention relates to a semiconductor memory device, e.g., a sense amplifier of an FBC (Floating Body Cell).
2. Related Art
Recently, there has been known an FBC memory device as a semiconductor memory device expected to replace a DRAM. The FBC is configured by an FET (Field Effect Transistor) that includes a floating body (hereinafter, also “body region”) provided in an SOI (Silicon On Insulator). The FBC stores therein either data “1” or data “0” according to the number of majority carriers stored in the body region.
A sense amplifier employed in the FBC includes a pair of sense nodes (hereinafter, “paired sense nodes”) that senses data with reversed polarities from each other. The sense amplifier also includes a latch circuit between the paired sense nodes. The latch circuit latches data from a memory cell onto the paired sense nodes via a pair of bit lines (hereinafter, “paired bit lines”) in a state where the respective data is logically inverted from each other. It is, therefore, necessary for the sense amplifier to invert the data latched onto the paired sense nodes before writing back the data to the memory cell when the latched data is to be written back to the memory cell.
To this end, the conventional sense amplifier includes a restoration-specific transfer gate between the paired bit lines and the paired sense nodes so as to reverse the connection relationship between the paired bit lines and the paired sense nodes during a data write operation from that during a data read operation.
Generally, the latch circuit is constituted by two transistors cross-coupled to the paired sense nodes, respectively. In order to ensure writing data to the memory cell, it is required to enhance a current driving capability of each of the transistors that constitute the latch circuit. In other words, a size (W/L) of each of the transistors that constitute the latch circuit should be enlarged. To enlarge the size (W/L), it suffices to expand a gate width W or to reduce a gate length L of each transistor.
However, during a data restoration operation, the data is written to the memory cell via both the transistors that constitute the latch circuit and the restoration-specific transfer gate. As a result, a total gate length is increased. Accordingly, it is required to increase gate widths W of the transistors and the transfer gate. This disadvantageously makes areas of the transistors larger.
If the areas of the transistors are larger, an occupation area of the sense amplifier is larger. Because the sense amplifier is provided for every pair of bit lines, the overall FBC memory device is disadvantageously made larger in size if the occupation area of the sense amplifier is larger.